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400GBASE-QSFP-DD-LR4 – What’s Inside?
Knowledge Base + 2023.11.29

400GBASE-LR4 – What’s Inside?

Now let’s take a look inside to see the main components of the transmission path of a 400GBASE-LR4.


The left side of this block diagram shows the 50G electrical lanes connecting to the host system into which the 400G DR4 module is installed. The blue block is circuitry (ASIC), referred to as a ‘gearbox’ the purpose of which is to combine 2 x 50G lanes into one 100G lane in the Tx direction and separate each 100G lane into 2 x 50G lanes in the Rx direction. The LR4 supports 4 x CWDM full-duplex 100G optical transmission lanes. The four CWDM wavelengths (1270nm, 1290nm, 1310nm, 1330nm) are multiplexed onto a single fiber in the transmit direction and de-multiplexed in the receive direction. This integrated CWDM Mux/DeMux allow the 400GBASE-LR4 to utilize a Duplex LC connector with which to connect to a duplex Single-Mode Fiber (SMF).

Standards Defining the 400GBASE-LR4

Several standards apply to define the attributes necessary to create multi-vendor plug-and-play 400GBASE-LR4 optical transceivers, as follows:

  • QSFP-DD MSA – This Multi-Source Agreement (MSA) defines the electrical and optical connections, electrical signals, power supplies, mechanical and thermal requirements of the pluggable QSFP Double Density (QSFP-DD/QSFP-DD800). It builds on the prior QSFP form factor, connector and cage system.

  • IEEE 802.3bs – This standard defines the 400GAUI-8 (GAUI – Gigabit Attachment Unit Interface) defining electrical clock and data interface between the 400G LR4 and the host system

  • OIF CEI-56G-VSR-PAM4 – The Optical Internetworking Forum CEI-56G-VSR-PAM4 (Common Electrical I/O, 56Gbps, Very Short Reach, Chip-to-Module, PAM4 Modulation) standard, or Implementation Agreement in OIF parlance, defines the SERDES (Serializer/De-serializer) function, including PAM4 modulation, for compatibility across the QSFP-DD to Host interface.